Gry Smith

Quest for the 10K Chip: Final Report

Part 1: Is this trip necessary? By Lou Covey New Tech Press First appeared in Print Version of Chip Design Magazine (June 2013)

At the Design Automation Conference in June 2012, Verilab’s JL Gray posed a perfectly unreasonable question: “Can you build a chip to verified prototype for less than $10,000 that an investor would want to back as a product?”  Over the past few months a variety of experts on the subject came to consensus and, as it turns out, the answer is yes and no. Yes, you can build one to prototype, but no, an investor would not find the product interesting. How about building a chip interesting to an investor for under $25 million, which Gary Smith, chief analyst for GarySmithEDA, calls the tipping point for investors.  Again, the consensus was in agreement: Yes, but not for at least 10 years... maybe 20.

DAC had a significant contingent of companies pushing FPGA prototyping tools and several pundits claiming that using FPGAs immediately reduce the cost of development.  In an interview a few months later, Smith concurred that people are making $10K chips with FPGAs and free tools “all the time,” but those tools did more good in developing chips at the 90nm and above node and nothing to reduce the cost of bringing a chip through manufacturing to market, which is the bulk of the cost, especially at the more advanced nodes. (link to Smith videos) That’s the rub, but progress is being made.

Reducing the overall cost of chips, from development to manufacturing, has been the goal of everyone from the smallest EDA company to the largest foundry.  But, every advance in process node means investment in even more expensive and potentially unproven technology.  Almost every EDA product release promises to reduce cost by $10 million, depending on the application, theoretically.

As early as 2009 the total overall cost for bringing an advanced chip to market exceeded $50 million.  Smith states that the cost has been reduced to as little as $28 million.  Much of that cost reduction, he identified as coming from three directions: effective and low-cost tool packages, the advancement of ESL tools raising the level of abstraction, and the return of independent design services reducing NRE costs.

It cost an average of $10 million to acquire enough EDA tools to do a decent job on a new chip 10 years ago. Smith said you can achieve success with packages below $20,000 now for chips at 90nm and up to 2 million gates.  Below that node, and above that gate count it gets dicey.

Raising the level of abstraction to ESL has been touted for years as the key to reducing overall cost, and the latest available tools, according to Smith, are just coming onto the market.  According to Karl Kaiser, vice president of engineering at Esencia, “ESL is the key to reducing engineering costs, which comprise the major financial barrier in the development of any truly innovative chip design.”

Kaiser pointed out that small companies, like Adapteva are using innovative tools as well as innovative ways of raising funds to develop new products (Maxfield article) to keep costs low.  Adapteva’s first chip to market cost less than $2 million.  But those cases are the exception rather than the rule.

Design services are rising to the forefront again to the level that Smith calls the niche, the “wild west” of the EDA industry with new companies coming to the forefront not only in Asia but in the US as well.

Josh Lee, CEO of Uniquify, a design service company, echoed Smith saying a design services company can not only simplify but standardize the design process, objectively evaluate what the right tool will be and compensate faster for specific tool weaknesses.  This eliminates a significant amount of NRE cost especially for an OEM that doesn’t specialize in chip design.  Several companies are divesting themselves of chip design departments and outsourcing the services to design firms.  Earlier this year TSMC added Uniquify as a design partner and LG Electronics selected the company for memory IP design.

A common thread, however, through all the comments and predictions on the issue of lowering the cost of semiconductors is NRE.  That boils down to the time it takes for an engineer or a team of engineers to coordinate and produce a design.  Tools can go so far. Outsourcing can go so far. Methodology, IP and design platforms can go so far.  None of them have even come close to dealing with one major problem: The amount of data engineers have to deal with.

There has been some discussion regarding the use of the cloud to allow EDA customers to use tools “as needed” rather than buying seats; and to use the cloud to coordinate disparate design groups worldwide.  Almost unanimously there is skepticism. “The cloud is an important aspect of IT,” said Smith, “but it can’t handle the high end computing problems.”  Lee concurred, “The cloud can be useful in EDA, but alone it will not help solve the problems of design.”

Or not... Stay tuned.

(Part 2: Enter Yotta Data Sciences, will appear later this week.  This article is unsubsidized and was produced in partnership with Extension Media.)